Logic Design Lead
• Define DFT (Scan, BSCAN and MBIST) methodology, architecture and implementation strategies for mixed signal IPs
• Work in close collaboration with design teams to implement DFT requirements.
• Define scan insertion and test mode STA constraints
• Perform pre-silicon ATPG and assist to bring post-silicon ATPG to production.
• Partner with DFT working group, RTL, Physical Design and release teams to deliver on time with quality
• Lead a team of DFTLogic design engineers
• BE / MS in Electronics Engineering with 8+ years of relevant experience
• Adept in DFT design and implementations
• Experience in mixed signal IPs will be a plus
• Prior experience on silicon level debug and tools flows will be a plus
• Strong in communication, leadership, investigation, problem solving and analytical skills
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
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INExperienced HireJR0202296BangaloreIP Engineering Group (IPG)
Logic Design Lead
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