The IAGS GTCHE (Graphics and Throughput Computing Hardware Engineering) organization is
responsible for the development of Graphics IPs & discrete GPU SOCs.
The FE-TFM team within GTCHE is responsible for providing methodologies for Best-In-Class RTL development, IP delivery, SOC integration and execution, and verification. The team develops and deploys these methodologies across all graphics IPs & SOCs. We are looking for a talented Front End Design Methodology Engineer to join our team. In this position, you will work on RTL design, integration & quality checks related flows across clusters, IP, Subsystems, SOCs. You will rapidly take features from concept to production and provide customer support, debug failures, and provide out of the box solutions.
- Understand and enhance the frontend design flows and methodologies across IPs and SOCs to identify key areas of improvement
- Provide user friendly solutions, to increase productivity of team
- Identify, define & publish the best practices for the various aspects related to RTL development, IP delivery, SOC integration, quality checks and back-end handoff
- 5 years experience in IP, SOC design and/or integration or RTL design experience.
- 3 Years of experience with system Verilog and familiarity with a range of internal and 3rd-party logic design tools
- Experience in FE development flows and tools (Verilog design language, VCS, SpyGlass etc.)
Inside this Business Group
Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level-not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.
IN JR0156994 Bangalore Intel Architecture, Graphics, and Software