IP Logic Design Engineer

Job Description
Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs. Participates in the development of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.

The team is looking for future technical leaders and experts. Position requires knowledge in digital logic design, computer architecture, and/or exposure to pre/post-silicon validation. Candidate will be responsible for logic design of different blocks in the Security IP team.

A member of this team would be responsible for defining and implementing the design in System Verilog, applying various strategies/tools/methods, checking the design for synthesizability, DFX, clock crossing, power, performance implications.

The candidate must work closely with Architects, Micro-architects and Validation teams in determining the proper implementation strategy for new design, defining and feedback on specifications, develop White Box Coverage plans, review design collateral for efficiency/coverage. The candidate may have the opportunity to engage with early prototyping (w/ FPGA, Emulation teams) and support SOC integration & DA tools team on behalf of the IP.

Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical leadership skills, passion for design/ tools and methodology and strong influencing skills. Must have strong orientation for Quality and `Commit & Deliver' and Drive Innovation/efficiencies and have strong strategic thinking to come up w/ paradigm shift solutions to critical design/validation challenges.

This is an entry level position and will be compensated accordingly.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

For Bachelor's applicants: This U.S. position is open to U.S. Workers Only. A U.S. Worker is someone who is either a U.S. Citizen, U.S. National, U.S. Lawful Permanent Resident, or a person granted Refugee or Asylum status by the U.S. Government. Intel will not sponsor a foreign national for this position.
You must possess a minimum of Bachelor's Degree in Electrical Engineering or Computer Engineering; Master's Degree in Electrical Engineering or Computer Engineering preferred.

1+ years of experience in Digital logic design tools and methodologies including:

  • System Verilog
  • Perl
  • VCS/Synopsys simulators
  • Lint, Synthesis
  • Clock Domain Crossing tools
  • DFX Scan and Power

Preferred Requirements:
  • Knowledge of critical PC IO subsystems (e.g. PCIe, USB, SATA, UART, SPI ...)
  • Knowledge of HW/SW Security mechanisms and cryptography
  • Knowledge of IO Controllers and Design and worked with standard buses / bridges such as AHB / OCP / AXI.
  • Knowledge of Low power / High Performance Designs and Practices.

Inside this Business Group
Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level-not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....
US College Grad JR0126095 Folsom

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