Hardware Logic Design Engineer
C2DG is looking for SoC DFT Scan Lead RTLer and Micro Architect
In this role, you will take a key part of C2DG DFT team design effort.
You will be In charge of planning, driving, defining RTL execution of SCAN RTL in all C2DG SoC, reporting to SCAN team manager.
- In charge of assuring Scan RTL is defined and implemented according to targets (to meet high-end SoC coverage, test time and DPM targets), working closely with all SoC's IPs' BE and FE teams.
- Technical leadership of 3 RTLers, delegating tasks and tracking
- Hands on Scan RTL coding and support to BE team
- Hands on RTL experience, leading execution and meeting tight goals.
- Experience with interacting, understanding and solving BE issues through RTL/uARCH changes
- Understanding and experience with DFT/SCAN RTL/BE flows an advantage
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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