Graduate Trainee (GT) : PCH Structural and Physical Design
Platform Controller Hub (PCH) is the silicon to enable critical interfaces to CPU and external system such as DMI/OPI/USB2/USB3/PCIE/SATA/AudioVisual/Security and Manageability Engine/CFIO etc. Candidate will be assigned to work on the next generation of PCH product alongside with a strong existing SD team, empowering the future experience of computing devices.
Candidate will require to IMPLEMENT the structural and physical aspect of PCH design such as Synthesis, Floor planning , Clock Tree design, Timing Budgeting and Clock Definition, Place and Route, RC-extraction, Full Chip Integration.
In addition, candidate will also need to VERIFY the structural physical design such as Power and Reliability Analysis, Functional/Structural Equivalency Check, Timing/Performance Verification, Timing-Noise Analysis and Layout Design Rules Convergence.
Candidate must possess a minimum of a Bachelor of Science degree in Electrical Engineering, and/or Engineering in a related field. Additional qualifications include:
- Fundamental architectural knowledge in microprocessors, computer system architecture and high speed design.
- Working level of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows
- Strong in issue driving and proficient in stakeholder management.
- A fluent communicator in both verbal and written forms.
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
MY Intern JR0116133 Kulim
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