Graduate Intern Technical

    • Bangalore, India

Job Description
Summary: Memory mapped BMC Interface, a POC project done to show case the new high bandwidth communication between BIOS & BMC communication, which can be available in early stages of BIOS. POC included updating both BMC & BIOS code to reflect the same.
Impact: Potential to intercept/use this interface in our next generation products. This also helps intern to work in core modules and this interface can be made as primary interface in future, thereby implementing Redfish Host interface on top of MMBI, this will enable interns to work on those future technologies.
Deliverables / Timeline: Proper implementation of POC and documentation. Time line : complete by Q1'21.

Project summary for MCTP work:
Develop validation framework for MCTP-PLDM protocol stack; Create test framework and automate test cases for add-in card manageability requirements.
Deliverable: Python based tool for validating MCTP-PLDM protocol stack.
Timeline: 9 months
Impact to SSE's business: The tool will enhance validation capabilities on the upcoming manageability standards
The intern will develop expertise on manageability standards/specifications, automation, Server domain, debugging complex platforms, Python and pytest frameworks.


M Tech

Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies-spanning software, processors, storage, I/O, and networking solutions-that fuel cloud, communications, enterprise, and government data centers around the world.

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IN Intern JR0129872 Bangalore

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