Full Chip Physical Design Engineer
Become a key member of a team participating in the physical design construction and integration and verification of a future Intel CPU! This position requires an engineer with broad physical design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team.
We are looking for a talented individual to drive the physical and timing convergence of a Full-Chip (FC) assembly of partitions. As a FC design engineer, you will perform floor planning, pin and feedthrough planning, repeater insertion, power grid generation, assembly of partitions, push-down partition collateral generation, constraints management and STA verification.
Given the need for executing multiple projects in parallel, you will be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
The ideal candidate should have an aptitude to work effectively with EDA tools and exhibit behavioral traits that indicate:
- Teamwork and be productive under aggressive schedules
- Excellent written and verbal communications skills
- Self-motivation and well organized
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have a Bachelors degree in Computer Engineering or Electrical Engineering and 7+ years of relevant work experience with: - OR - a Masters degree in Computer Engineering or Electrical Engineering and 5+ years of relevant work experience with:
- Integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
- Synthesis of a digital logic block, which was integrated into a large SoC or IP
- PV convergence (including static timing and power analysis)
- Scripting in TCL and one or more additional interpreted languages (e.g. Perl, Python)
7+ years experience in:
- Intel CPU/Microprocessor design
- Design of a high-speed CPU core logic block
- People management of a 4 -10 person team
Inside this Business Group
The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
US, Texas, Austin
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
US Experienced Hire JR0154150 Hillsboro Devices Development Group (DDG)
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