Job Description
Job Description: In this position you will be part a world class IP physical design team developing groundbreaking high-performance GFX targeting High End Graphics, Gaming, Artificial Intelligence, Media processing, and other applications. This is a great opportunity to join a talented team, early in the product lifecycle and will include lots of innovation in RTL2GDSII implementation of multi-million gate designs in advanced process nodes, both internal and external. As a Syn/PD Methodology Lead, your responsibilities may include, but not be limited to:

• Defining and instrumenting Methodology on a wide range of implementation flows, including :
  • Synthesis with Synopsys Design Compiler DCT/FC-FE
  • DFT, Scan Insertion, and coverage analysis
  • Floorplanning with ICC2-DP and internal FP solutions
  • Multiple Power Domain implementation using standard Power Formats UPF/CPF
  • Place and Route and clock tree synthesis with Synopsys ICC2/FC-BE
  • Post-Route flows using well-formulated recipes for best in class power & performance  

• Engaging closely with design teams on these complex IPs to understand the design & convergence challenges, and formulate suitable implementation recipes with a focus on PPA & TAT optimizations
• Working with 3rd party EDA vendors to resolve tool/flow issues and drive improvements and innovation in design convergence through deployment of next-gen capabilities

• Self-motivator with strong problem-solving skills
• Strong leadership skills with ability to mentor junior designers
• Excellent interpersonal skills, including written and verbal communication
• Ability to work as part of a team and collaborate in a high-paced atmosphere

• Mtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 7-15 yrs of relevant RTL2GDS experience
• Demonstrated capability in methodology development and design enablement of complex multi-million gate designs, in areas of Synthesis, Floor-planning, Power-planning, Placement, CTS & Routing is a must
• Expertise and in-depth knowledge of industry standard EDA tools (Synthesis, Floorplanning, P&R) and ASIC design flow is required
• Multi-voltage scenarios design handling knowledge is expected .  
• Proficiency in scripting language, such as, Perl & Tcl required