- Bangalore, India
Develops and supports design for test (DFT) structures. Determines design for test approaches and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry. Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns. Knows about failure mechanisms in silicon production and creates test algorithms. Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.
M Tech VLSI with 7-8 Years of experience. Strong knowledge of DFT architectures & methodologies which includes Scan, ATPG, MBIST, BSCAN, JTAG, Boundary scan etc Strong knowledge of SoC methodology and tools (VCS, Mentor ATPG experience is a plus). Knowledge of Physical design is advantageous. Experience in Verilog & System Verilog, RTL design Strong debug skills and experiences in Perl & TCL scripting are a must. Strong Communications skills and the ability to work with minimum supervision In addition, this position requires interaction and fulfilling the requirements of Intel's post-silicon/ATE teams, Silicon Debug and understanding HVM (High Volume Manufacturing) requirements
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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IN Experienced Hire JR0140540 Bangalore
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