Chipsets Logic Design Engineer
- George Town, Malaysia
Seize the opportunity to work with the team responsible for pre-silicon logic verification of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team is part of the Chipsets Silicon Group (CSG) within Client Engineering Group and are responsible for developing Soft IPs, Subsystems and Gaskets for client and server chipsets. As a Chipsets Logic Design Engineer, a typical day may include, but is not limited to: - Performing logic design, Register Transfer Level (RTL) coding, and formal verification - Participating in the development of Architecture and Microarchitecture specifications for the Logic components. - Providing IP integration support to SoC customers and represents RTL team. - Performing tools and flows to qualify the logic implemented, such as RTL/DFx linting, clock/reset domain crossing check, synthesizability check to meet design QoR, timing constraint definition and review, gate-count/power optimization, etc. You are: - An excellent communicator - Extremely organized - A team player who loves to collaborate - A strong technical leader who communicates well with great influencing skills - Passionate for design/tools and methodology - Someone who meets their commitments - Motivated - Self-driven - Someone who wants to make a difference through technology We are: - Open to new ideas and methodologies - A collaborative team demonstrating the best teamwork across Intel - Here to help you succeed - People who want to do innovative things If your skillsets align with our needs, we will provide you a great path to maximize your positive impact on the world.
The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science, or equivalent. o 6 years of relevant logic design/pre-silicon verification experience with multiple project cycles o 6 years of logic design/pre-silicon verification experience with various tools and methodologies including but not limited to: - System Verilog - Python/Perl/Shell scripting - VCS/Synopsys simulators - interactive debugger - RTL model build - testbench development - power-aware simulation - design-for-test - design-for-verification - coverage-based random constraint simulation o 3 years of PC Architecture experience o Capable in developing RTL and micro-architecture based on High Level Architecture specifications o VLSI or Structural and Physical design flow/methodology experience o Power management, UFS, SPI, USB, PCI express or any industry standard BUS protocol experience o Strong analysis, debugging skills, and creative in problem solving
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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