Backend Timing expert lead

Job Description
We are looking to recruit a senior technical lead and manager for the Intel Core IC and Timing convergence team.
It is a small central team, of about 4 engineers.
This team is in-charge of Intel core timing convergence, and its related interface with the SOC.

It runs the day to day execution, sets the project mid-targets and defines the MOW on the way to a successful TI.
The team defines tasks and methodologies for all the Core design people through a 2nd level timing owners (called STOs ~10 engineers) which you will lead in a marix mode.
Through them, all Core BE design engineers are working on their blocks for a high quality timing convergence.

Intel cores, designed by the team, is the most important part in Intel SOCs for both client and server markets. It is the biggest single IP contributor for Intel revenues.
Haifa design site, is the leading Intel design site in the world.


  • B.Sc. In Electrical engineering or Computer engineering from a leading institute
  • >8 years of hands on BE design experience in high speed VLSI design
  • Expert level of knowledge in static timing analysis
  • Good knowledge in IC design and modeling
  • Leadership traits, initiating and ability to drive innovative ideas for efficiency improvements
  • Experience in timing analysis in section/FC/SOC level - High advantage

*** Please be informed that Intel is proactively trying to find candidates for a this position and that this position may not be available at this time

Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

IL JR0091500 Haifa

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