Atom CPU Full Chip Physical Design/Timing Verification Engineer
- George Town, Malaysia
Become a key member of a team participating in the physical design construction and integration and verification of a future Intel CPU. This position requires an engineer with broad physical design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team. We are looking for a talented individual to drive the physical and timing convergence of a Full-Chip (FC) assembly of partitions.
As a Full Chip design engineer, you will perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation, assembly of partitions, push-down partition collateral generation, constraints management and STA verification. Given the need for executing multiple projects in parallel, you will be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
The ideal candidate should have an aptitude to work effectively with EDA tools and exhibit behavioral traits that indicate:
- Ability to work well in a team and be productive under aggressive schedules
- Excellent written and verbal communications skills
- Self-motivation and well organized
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the
minimum requirements and are considered a plus factor in identifying top candidates.
- Must have either BS or MS in Electrical Engineering or Computer Engineering
- Minimum 8 years of experience in
- CPU physical design and timing verification
- Synthesis/APR flows on multi voltage high frequency designs including custom polygon editing
- Tcl scripting
- Noise, cross-talk, OCV analysis.
- Floorplanning and physical design and timing closure.
- Formal equivalence, DRC/LVS, IR and electro-migration checks
- 10+ years of experience with the above skill sets
- Experience with Fusion Compiler, DCT, DCE, ICC2, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT
Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
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