Analog Design Engineer (PLL IP)

Job Description
You will be joining an expanding analog/mixed-signal PLL team involved in design and development on cutting-edge Intel process development nodes.
Your responsibilities will include but not be limited to:
The candidate should have experience in Analog and Mixed Signal Design with focus on PLLs and clocking circuits.
Strong fundamentals of CMOS design, passive RC circuits, switched cap circuits are a must for this role.
The various task involves, circuit design, validation, mixed signal validation, and reliability validation.
Exposure to PLL designs (either Charge-Pump based or ADPLLs or both, Fractional-N PLLs, spread-spectrum PLLs, etc.)
High speed digital circuit design and analysis with timing and flow closure.
Digitally assisted analog circuit and techniques.
The candidate will be responsible for the High speed, low power, and reliable analog and digital circuits for various areas of PLL.
Good knowledge of control systems, band gaps, bias, op-amps, LDOs, feedback and compensation techniques.
Experience in LC VCO/DCO design. Good exposure to performance parameters of VCO as well as complete PLL architecture."


Candidate should possess at least a Master of Science degree in Electrical Engineering or equivalent.
Strong academic background required in CMOS semiconductor device physics and silicon processing.
Relevant coursework in CMOS digital, analog, and I/O circuit design Knowledge of transistor-level circuit simulation tools such as SPICE
The following preferred qualifications would be an added advantage:
5-10 years of experience in Circuit Design.
Familiarity with CMOS transistor and semiconductor device layout methods.
Experience using custom design environments such as Cadence design automation tools (ADS, Analog Artist, or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools.

Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

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