Senior Design Verification Engineer (Field Progammable Gate Array)

Senior Design Verification Engineer (Field Progammable Gate Array)

Job Description:

Hewlett Packard Enterprise (HPE) is an industry leading technology company that enables customers to go further, faster. With the industry's most comprehensive portfolio, spanning the cloud to the data center to workplace applications, our technology and services help customers around the world make IT more efficient, more productive and more secure.

HPE Aruba is one of the fastest growing businesses within HPE and offers opportunities to experience various leading edge technologies such as Bring Your Own Device (BYOD), Cloud and Software-Defined Networking (SDN). One can grow his or her career in a variety of different verticals, all the way from the cutting edge tablet business to high-end enterprise business. Here, employees productize and innovate to solve real world customer challenges.

We are currently looking for a dynamic, talented and innovative individual to be part of our high-speed digital circuit designers developing state-of-the art networking products. Explore your career options with HPE Aruba, together we will do something amazing.

Roles and Responsibilities:

  • Responsible for end-to-end FPGA verification, from subsystem to full chip level verification. Will design, develop and use simulation based verification environments at sub system and full chip level.
  • Develop test environment, test plan and test cases based on FPGA and product specification. Require to execute test cases, debug, resolve issues to meet full features in functional requirements.
  • Collaborate with other technical contributors on system validation and integration testing with hardware.

Education and Experience Required:

  • Bachelor's or Master's Degree in Electrical Computer Engineering or equivalent.
  • Minimum 5 years of hands-on experience with FPGA or ASIC verification.
  • Strong experience with Verilog and development of system Verilog test benches for full chip test bench environments with Cadence IES, Questasim to test full FPGA chip.
  • Proficient developing directed tests and constraint random tests(UVM test suite) environment and a strong understanding of system Verilog assertions.
  • Experience using formal verification tools (eg:Cadence Jasper Gold) will be an advantage.
  • Experience with Altera and Xilinx FPGA synthesis and development environment is an advantage
  • Understanding of FPGA architecture and good logic design fundamentals
  • Familiarity with verification of common interfaces (PCI-Express, DDR3/4, I2C, SPI, RS232, MDIO, XAUI).
  • Exposure to integration and debugging tools, such as oscilloscope and logic analyzers is an advantage.
  • Self-driven and able to work independently in a fast moving dynamic environment.
  • Good communication and inter-personal skills to enable global and cross-functional engagements, plus ability to read, comprehend and explain engineering drawings and technical documents.



Job Level:


Hewlett Packard Enterprise is EEO F/M/Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to the use of arrest and conviction records, including the San Francisco Fair Chance Ordinance and similar laws and will consider for employment qualified applicants with criminal histories.

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