Digital Design Engineer

Facebook Reality Labs, or FRL, focuses on delivering Facebook's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
We are growing our Digital Design Engineering team within AR Silicon and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using your digital design skills to implement and contribute to development and optimization of state of the art SoCs as well as vision/sensing algorithms. You will also support the Silicon Architects in developing and implementing the next generation custom and semi-custom mixed signal ICs to drive our industry leading virtual and augmented reality systems.
This role can be based in Redmond, WA or Menlo Park, CA.

RESPONSIBILITIES

  • Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
  • Understand our in-house IPs needed and how they need to be integrated, connected and verified
  • Drive the top-level µArchitecture definition and develop the necessary RTL
  • Drive the chip-level integration, verification plan development and verification
  • Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
  • Support the test program development, chip validation and chip life until production maturity
  • Work with FPGA engineers to perform early prototyping
  • Support hand-off and integration of blocks into larger SOC environments
  • Assist with Algorithm analysis, verification and improvement
  • Contribute to ASIC digital architecture, design and verification
  • Ability to communicate clearly
MINIMUM QUALIFICATIONS
  • 2+ years of experience as a Digital Design Engineer
  • Experience in RTL coding, synthesis and/or SoC Integration
  • Experience in digital design µArchitecture
  • BS Electrical Engineering/Computer Science or equivalent experience
PREFERRED QUALIFICATIONS
  • 3+ years of experience as a Chip Lead
  • System Verilog OVM/UVM experience
  • Python (or similar) scripting experience
  • Experience in SoC integration and ASIC architecture
  • Experience in DFT/Testability requirement and test program definition
  • Experience using High Speed interfaces like PCIe, USB, MIPI
  • Master's degree in EE


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