ASIC Engineer

    • Sunnyvale, CA

Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities - we're just getting started.

Facebook is hiring ASIC Engineers within our Infrastructure organization. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications.

  • End-to-end SoC/ASIC development:
    • Firmware and driver development, front-end and back-end standard cell ASIC development (including algorithm and architectural modeling, silicon architecture, micro-architecture, RTL development, Design Verification, FPGA emulation, co-simulation, simulation acceleration, synthesis, and post-silicon validation)
    • Cross-functional collaboration and partnering with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts
    • Soft and hard IP identification, selection and IP licensing
    • Define, debug, implement and deliver system solutions around purpose built ASICs
  • B.S. or M.S. degree in Computer Engineering, Computer Science or Electrical Engineering
  • Track record of first-pass success in ASIC and Systems Development
  • Experience in one or more HDL language (System Verilog, Verilog), and one or more scripting language (TCL, Python, Perl, Shell-scripting)
  • Experience with SoC design methodologies that involve multiple clock domains, clock power management and system debug in addition to experience in low power design, tools and methodologies including power intent UPF specifications
  • Bit Accurate and Transaction Accurate Modeling: experience in C/C++/SystemC
  • Design Verification: experience in one or more Verification language (UVM, System Verilog) creating test plans and defining coverage
  • Experience working across multiple projects
  • Hands-on experience with Standard Cell ASIC development from Architecture through to GDSII release (including pre-silicon emulation and co-simulation) and post-silicon
  • 3+ years of silicon development experience
  • Early stage startup experience within silicon development
  • Familiarity with HLS
  • Familiarity with System Verilog Assertions
Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law.Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at

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