Senior ASIC Engineer

Come work at a place where innovation and teamwork come together to support the most exciting missions in the world!

Our Employees

Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work. They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset

Position Summary:

Develop verification components in SystemVerilog UVM for complex designs. The DUT (Design Under Test) can be a block level module, where meticulousness is required. Or integrated level that requires more of a system view.

As a part of a small team, multitasking and flexibility is necessary. Tasks may change fast and more than one task is usually executed in parallel.

Attractions of the Job:

In this position, you will develop cutting edge FPGA designs. As a part of a small team, you will have a significant role. You will have the opportunity to accelerate your skills and responsibilities. We encourage initiative and even expect it.

Primary Responsibilities:

  • Write HDL design in SystemVerilog (50%)
  • Define micro architecture.
  • Write RTL code.
  • Run simulations and debug results.
  • Run synthesis and P&R tools (Quartus, Vivado). Analyze results to achieve timing closure.
  • Write verification environment in UVM (30%)
  • Define verification environment.
  • Write UVM code.
  • Write a test plan.
  • Write functional coverage.
  • Run simulations.
  • Learn other skills and take responsibility (20%)
  • Every team member is expected to be able to do, both design and verification.
  • Take initiative, suggest ways to improve. Develop tools and scripts to accelerate design cycle.

Other Responsibilities:

  • Responsible for upholding F5's Business Code of Ethics and for promptly reporting violations of the Code or other company policies.
  • Performs other related duties as assigned.

Knowledge, Skills and Abilities:

  • Design experience is a must.
  • Knowledge in OO programing is a must.
  • Knowledge in verification is desirable.
  • Knowledge in SystemVerilog is desirable.
  • Good communication skills. Ability to work as part of a team.
  • Self-learning. Ability to work independently.
  • Good English. Ability to communicate in English, both verbally and in writing is a must.

Qualifications:

  • 4-8 years of professional experience.
  • BSEE or equivalent.

Physical Demands and Work Environment:

  • Duties are performed in a normal office environment while sitting at a desk or computer table. Duties require the ability to utilize a computer, communicate over the telephone, and read printed material.
  • Duties may require being on call periodically and working outside normal working hours (evenings).
  • Duties may require the ability to travel.

Equal Employment Opportunity

It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability, marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws. This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. Reasonable accommodation is available for qualified individuals with disabilities, upon request.


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