Design Verification Engineer
Contribute to verification infrastructure development for complex ASICs.
Develop test plans based on functional requirements, as well as applicable standards requirements.
Develop System Verilog/UVM based environment components, for use in the verification of DSP algorithms, ARM-based Control Planes, and/or Networking Protocols.
Responsible for the definition, development, and execution of self-checking tests.
Cross-functional support of emulation, firmware development, post-silicon validation, and system integration activities
Masters degree desired, Bachelor's degree in CS/EE is required.
8+ years of relevant experience in ASIC verification field.
Fluent in System Verilog/UVM and scripting languages such as Python.
Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
Solid communication skills and ability to interact with cross-functional teams
Previous experience with ARM Processors, AMBA/AXI, DSP, or Networking a plus
Previous experience with ARM Processors, AMBA/AXI, DSP, or Networking a plus but not required
Annual Hiring Range/Hourly Rate:
$126,000.00 - $154,000.00
Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.
US-CA-San Jose, California (eInfochips)
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.(Arrow EEO/AAP policy)