Synthesis/UPF Methodology Engineer
- Cupertino, CA
Posted: Jun 4, 2021
Role Number: 200208829
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers.
- Expertise in synthesis, UPF, timing analysis and closure.
- Experience in creating or improving low power synthesis methodologies.
- Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
- Experience with scripting languages like Perl or Tcl or Python.
- RTL logic design or implementation experience on multi-million gate ASICs will be a plus.
- Strong communication skills to effectively communicate across all internal groups.
- Attention to detail and desire to learn.
As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design and integration: - Drive all front end integration activities like Synthesis, UPF, Logical Equivalence, ECO, etc. - Work closely on methodology for improving synthesis QOR. - Work on Low power design, writing UPF's and power intent verification at chip level (VCLP). - Work on RTL integration, timing constraints, synthesis of designs. - Work closely with other engineers that are members of the SOC Design, CAD, STA, Power, and Physical Design teams.
Education & Experience
BS or MS in EE, EECS, or CS is required.
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