SoC Physical Design Engineer, Timing - STA
- Beaverton, OR
Posted: Jun 26, 2020
Role Number: 200087495
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, large subsystems. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll craft and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role, you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.
- Deep understanding and familiarity with all aspects of timing of large high-performance SoC designs in sub-micron technologies
- Timing Margin fundamentals from synthesis to signoff is required.
- Do you have a proficiency in STA with methodologies for timing closure, including a deep understanding of noise, cross-talk, and OCV effects, among others.
- Familiarity with circuit modeling, including SPICE models and worst-case corner selection.
- Your demonstrated ability to program with Perl, TCL will serve you well.
- We value your ability to create timing flows using industry standard tools.
- Your depth of expertise in STA on large, complex designs and Multi-Scenario Timing Closure is invaluable to our team.
- Familiarity with ECO techniques and implementation is preferred.
- Good communication who can accurately describe issues and follow them through to completion. Your attention to details will be instrumental to success.
Work with design teams to understand and debug constraints, facilitate logic changes to improve timing. With the Physical Design and Logic Design teams you will highlight issues and establish standard methodologies. Help craft timing ECO's for project tapeout. Create/maintain scripts and methodologies for analysis and runs. Document and help with guidelines/specs. Deep analysis of timing paths to identify key issues. Implement timing infrastructure. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hear from you!
Education & Experience
MSEE or equivalent is required
Back to top