Senior PLL Designer
Posted: Aug 2, 2019
Weekly Hours: 40
Role Number: 200001948
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and especially talented Senior PLL Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Apple Silicon Engineering is seeking senior PLL designers to lead the next generation PLLs for Apple's world-leading systems-on-chip (SOCs). You will be part of a growing analog/mixed-signal team involved in design and productization on leading-edge CMOS process technology nodes.
- - The ideal candidate should have proven taking chips to production with experience in the following areas: Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs, Digital PLL techniques, etc., for SOC and SERDES applications.
- - PLL loop design to optimize for phase noise/jitter, lock time, reference spur, area, power.
- - High speed digital circuit design and analysis (e.g., STA, formal verification).
- - Digitally assisted analog circuit and techniques (e.g., calibration, adaptation, fast lock, etc.).
- - Proven knowledge of low noise design, high precision design, band gaps, bias, op-amps, LDOs, feedback and compensation techniques.
- - Experience in VCO design including but not limited to LC VCOs.
- - Lab and ATE test plans, and measurement for characterization and volume production.
In this role, the key responsibilities are the following: Lead PLL team members in definition, execution, tapeout and silicon bring-up activities. Understand system level requirements to craft overall PLL specifications. Work with team in driving architectural modeling and decisions, and block-level requirements for analog and digital blocks. Work closely with mask design team to implement layout view of designs. Drive top-level spice and mixed-mode simulations to validate top-level integration. Lead efforts in pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements. Define production/bench-level test plans for post-silicon characterization. Work with lab engineers in taking lab measurements to validate IP. Review ATE and lab test results to resolve yield issues and drive bug fixes. Work with system teams in system bring-up and debug. Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.
Education & Experience
Masters Degree in Electrical Engineering with 8+ years in related area of expertise or PhD with 5+ years experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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