Power Delivery Modeling Engineer
- Cupertino, CA
Posted: Aug 24, 2021
Role Number: 200207879
Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. You will be part of a silicon design group that is responsible for crafting state-of-the-art ASICs. We are pursuing a motivated applicant to work on the modeling of power delivery and power dissipation, current demands and current profiles of SOC IPs, along with the corresponding voltage profiles and frequency of modern SOCs. The role involves engaging with the SOC architecture and design teams, working with the power modeling team, collaborating with the package, PMIC and system design teams to model the current profiles for various IPs of the SOC, and the voltages required to achieve the target frequencies. The job also involves partnering with the lab and silicon characterization team on correlating models to the HW data.
- We are looking for applicants with 3+ years of demonstrated ability, proven programming skills and understanding of low-power digital design and power fundamentals, including:
- Understanding of SOC power modeling and current profiles.
- Understanding of electrical properties of on-die PDN, power gating, package and system power delivery.
- Strong skills in scripting, programming and numerical methods.
- Understanding fundamentals of VLSI design and CMOS technology.
- Extensive background in EE.
- Strong team playing and excellent communication skills are essential.
Imagine yourself collaborating with many fields, playing a decisive role of getting functional products to millions of customers quickly! You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers and be involved in HW/model correlation efforts of mobile SoC design. Your main responsibilities will be: • Modeling of the power delivery networks, including on-die power gating and in-rush current profiles. • Modeling of the current profiles and peak current demands of various IPs. • Establishing voltages for DVFM states of IPs, including CPUs, Graphics, Neural Engines, compute accelerators, media, caches and fabric. • Modeling power dissipation for customer use-cases. • Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network. • Interacting with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage guard-bands. • Working with the power lab and test teams to correlate models to HW data.
Education & Experience
MSEE or Ph.D. required.
Back to top