PHY Systems & Algorithm Engineer
- Cupertino, CA
Posted: Mar 26, 2019
Weekly Hours: 40
Role Number: 200001291
Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Process Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if need be. A project might call for designing new equipment, developing new materials, or even building a new factory to bring a visionary idea to the real world. Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before imagined. In this technical role, you will be at the center of a silicon design group responsible for physical layer system and algorithm design for state-of-the-art wireless SoC products.
- This is an individual technical contributor role that requires you to design signal processing and wireless communications systems.
- In-depth knowledge on wireless communication systems (OFDM/MIMO, etc), hands on experience on lab testing & characterization is a plus.
- Deep understanding of communication theory & signal processing related algorithms design (such as timing recovery, signal estimation and detection, automatic gain control, RF impairment estimation and correction, channel estimation, equalization, coding theory, etc.)
- Experience with Matlab or Python and/or C/C++ for algorithm development, modeling, and simulation.
- Experience and knowledge on High Level Synthesis (HLS)
- Experience on bring up real silicon in lab, be able to use lab equipment (such as spectrum analyzer, signal generator, power meter, etc).
- Deep understanding in existing wireless communication protocols: LTE/WCDMA/GSM, 802.11a/b/g/n/ac/ax, 802.11ad or Bluetooth/BLE
Design and simulate state-of-the-art physical layer wireless communication system algorithms for very high data rate applications. Implement fixed-point models and perform detailed performance investigation to allow performance sign-off and enable RTL bit-exact development. Work with digital designers to realize these algorithms with power and area efficient digital implementations. Test and characterize real silicon in lab.
Education & Experience
MS with 10+ Years experience or Ph.D. with 7+ Years experience.
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