Skip to main contentA logo with &quat;the muse&quat; in dark blue text.
Apple

PHY Design Verification Engineer

Cupertino, CA

Summary Posted: Oct 14, 2022
Role Number:200203333

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional wireless products to hundreds of millions of customers quickly.

Want more jobs like this?

Get Software Engineering jobs in Cupertino, CA delivered to your inbox every week.

By signing up, you agree to our Terms of Service & Privacy Policy.


Key Qualifications

2+ years of verification experience of wireless/wired communication block/subsystem.
* Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
* Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
* Experience of using Matlab/C reference model and bit-accurate verification a plus.
* Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
* Proficiency in shell and Perl scripting, Python skills a plus.
* Experience of Palladium/FPGA validation a plus.
* Should be a team player with excellent communication skills, self-motivated and well organized.

Description
- Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. - Build block/subsystem level test benches with reference model, using best in class DV methodology. Architect test benches with maximum reusability in mind. - Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found. - Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. - Support PHY subsystem validation using Palladium and/or FPGA.

Education & Experience
BS required, MSEE preferred

Additional Requirements

Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

Client-provided location(s): Cupertino, CA, USA
Job ID: apple-200203333
Employment Type: Other

Company Videos

Hear directly from employees about what it is like to work at Apple.

This job is no longer available.

Search all jobs