Posted: Oct 5, 2021
Role Number: 200052038
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. This exciting role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for realizing the complete electrical analysis closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration.
- Experience planning, implementing, and analyzing power delivery networks. Emphasis will be with on-die high frequency power delivery, but exposure to off-die concepts and models is required.
- Your expertise working with different types of power-gated delivery techniques are crucial, including distributed and ring methods. Experience with in-rush current analysis and mitigation techniques recommended.
- Showcase your experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios.
- Experience with fundamentals of Signal/Power Integrity checks for Electromigration and Static Noise checks. Circuit design and simulation background a plus, but not required.
- Background with Power Integrity analysis methodologies including Static IR and Dynamic Voltage drop checks, involving both Vectorless and Vectored approaches.
- We value a proven track record in all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Your depth of expertise with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies will serve you well.
- From a CAD tool perspective, prior experience with global power integrity tool (e.g. Redhawk, Voltus) is required. Additional experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification Flows are a plus.
Work closely with the Physical Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA). Drive definition of on-die power switch topology, wake-up schemes, and in-rush control. Collaborate with internal teams to drive bump map, custom RDL routing, and package design/optimization. Develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges. Perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hear from you!
Education & Experience
MSEE or equivalent is required