GNSS PHY/RTL Design Engineer

    • San Diego, CA

Summary

Posted: Jan 23, 2020

Role Number: 200144147

Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a GNSS PHY/RTL Design Engineer, you will be at the center of the silicon design group with a meaningful role getting functional products to millions of customers quickly. Wouldn't you love a dynamic yet challenging role as a PHY/RTL Design Engineer here at Apple?

Key Qualifications

  • 7+ years of hands-on experience and 5+ years of experience with power efficient GNSS PHY design
  • Good knowledge in modern design techniques and energy-efficient/low power logic design
  • Solid background in computer architecture including one or more of the following:
  • Bus fabric, especially APB/AHB/AXI
  • Tiered memory systems
  • System debug architecture
  • Power management with multiple power domains
  • Integer and floating-point numeric units
  • High-speed data path and control units
  • Track record of bringing logic designs into mass production
  • Ability to work well in a team and be productive under aggressive schedules
  • Excellent communication skills and self-motivation/organization
  • Experience with FPGA and/or emulation platform desired
  • Ability to drive strong production test/QA methodologies a plus


Description

In this role, you will develop signal processing intensive design for GNSS SoCs, including: Microarchitecture definition IP integration, RTL logic design, and verification support Running tools to ensure lint-free and CDC clean design Synthesis and timing constraints Collaboration with system/algorithm and firmware team to ensure performance and power efficiency

Education & Experience

BS is required, MSEE/PhD preferred

Additional Requirements


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