DFT Design Verification Engineer
- Cupertino, CA
Posted: Aug 27, 2021
Role Number: 200066337
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers.
- 2-5 years of experience in large processors and/or SOC designs.
- Hands-on experience in directed or random verification, coverage analysis and assertions.
- Proficient in scripting languages such as Perl, Python or Tcl.
- Excellent skills in problem solving, communication and desire to seek new challenges.
- Good knowledge of general logic design, and exposure to DFT is a plus.
In this highly transparent role, you will be at the center of a System On Chip DFT Verification effort with a critical impact on getting functional products to millions of customers quickly. As a DFT-DV engineer, you will have responsibilities spanning various aspects: - Reviewing Architecture and Design Specifications. - Extracting design features, and developing attributes and verification plans. - Working with designers to verify DFT implementation and run various checks. - Implementing test benches, generating directed/constrained random tests. - Debugging failures, running gate level simulations, tracking bugs and closing coverage. - Handling schedules and supporting multi-functional engineering effort. - Assisting in verification flows, automation scripts and regressions. - Working with test engineers to bring up test patterns on silicon.
Education & Experience
- BS/MS in EE/CE is required.
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