DFT Design Verification Engineer
- Cupertino, CA
Posted: Jun 17, 2021
Role Number: 200003677
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next extraordinary Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. In this highly transparent role, you will be at the center of a SoC design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly
- You will have 0-5 years of relevant experience in large processors and/or SOC designs.
- System On Chip DFT Verification effort includes BISTed rtl verification (Built In Self Test repair loading for memories).
- Experience in DFT (including Silicon debug) is desirable.
- A deep understanding of, and problem solving skills in, Logic design and Synthesis & Timing will be a plus.
As a DFT engineer: Developing and implementing DFT architecture. Working with designers and DV team to integrate DFT implementations, verify and review verification coverage. Also run various checks. Balancing schedules and supporting multi-functional engineering effort. Working with test engineers to bring up test patterns on silicon. Working with rest of the team to document DFT specifications. Generating structural test patterns and analyzing and improving coverage.
Education & Experience
BS/MS in EE/CE is required.
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