DDR Lead Design Verification Engineer
- Cupertino, CA
Posted: May 19, 2021
Role Number: 200201389
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Do your life's best work here at Apple! This role is for a DV engineer who will enable bug-free first silicon for the mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
- Deep knowledge of SystemVerilog test-bench language and UVM
- Experience developing scalable and portable test-benches
- Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations
- Deep experience with different DDR protocols including Low power version
- Should have been in technical lead position
- Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc.
- Working knowledge of one of the scripting languages: Python, Perl, TCL
In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are expected to: Lead and develop detailed test and coverage plans based on the micro-architecture. Drive verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment and work closely with analog team to ensure overall bug-free mixed-signal design.
Education & Experience
MSEE Degree+ 3 years of industrial experience BSEE Degree+ 5 years of industrial experience
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