Codec Modeling Architect - Platform Architecture
Posted: Feb 3, 2020
Role Number: 200104626
Do you love crafting elegant solutions to highly complex challenges? Are you a big-picture visionary who understands how each element affects all the others? At Apple, our Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to design how all of our technologies work in unison. In this role, you will be part of the Media IP Architecture team to define, architect, design, implement and deploy models for HW media IP including video encoder, decoder, video and display processors.
- 5+ years in developing models for hardware validation
- Domain expertise in hardware video IP including video codecs, video and image processing units
- Experience developing C/C++ bit accurate models for hardware verification
- Experience working in a chip development environment with RTL designers and verification engineers
- Experience integrating IP models into chip simulation platforms
- Experience debugging complex models
- Experience working with C-modeling tools, including C/C++, SystemC and scripting languages such as Perl and/or Python
- Knowledge of video coding standards including H.264, HEVC
- Preferred knowledge of video processing algorithms
As a Codec Modeling Architect, you will be responsible for developing, integrating and maintaining software models for various video encoder, decoder and display/video processing IPs. Responsibilities will include: - Define, document and implement C/C++ bit-accurate and transaction level models with chip and media IP architecture teams - Collaborate with design and verification teams to define C-model interfaces for validation and debug - Work with the SOC performance team to model memory latency and IP performance - Work with the SOC modeling team to integrate the IPs in full SOC models - Develop and maintain architecture test cases and automated workflows to verify the correct functionality of the models
Education & Experience
BS/BEng/MS is required.
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