Cellular SoC Performance Modeling Architect

    • Cupertino, CA

Summary

Posted: May 6, 2020

Role Number: 200169515

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly! Bring passion and dedication to your job and there's no telling what you could accomplish Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Are you ready to join our team and revolutionize System-on-Chip development? In this role, you will be a member of a Cellular System-on-Chip (SoC) architecture team, working with hardware and software engineering groups to craft the architecture of Apple's future devices. The role will focus on architecture definition, exploration and modeling of the memory subsystem, caches, interconnection networks, fabrics, and Quality of Service (QoS) solutions for Apple's Cellular chips. The position calls for independent development, definition, performance modeling, documentation, and collaboration with design/software teams. We are looking for SoC architects with a passion to develop and detail new and innovative ideas and model them in C++ to demonstrate their value and impact.

Key Qualifications

  • You will have experience/skills in several of the following areas:
  • SoC performance analysis by developing transaction-level models (TLM) and running case study simulations.
  • C++ object-oriented programming, debug, and testing.
  • 4G/5G modem system engineering.
  • Cellular use cases, their HW/SW data flows and bandwidth/latency requirements.
  • ARM CPU memory access characteristics and performance requirements.
  • AXI fabric design, high-bandwidth vs. low-latency performance trade-offs.
  • DRAM controller design and quality of service (QoS) solutions.
  • PCIE protocol and controller design.


Description

You will develop C++ transaction-level models and use them to generate simulation results that will drive the hardware architecture and RTL design decisions for Apple's Cellular SoCs. Your work will be highly visible and critical to delivering the best performance and power efficiency in Apple's future products. You will be expected to collaborate with all the hardware and software teams that are part of Apple's SoC development: - Work with multi-functional teams to develop architectural solutions. - C++ performance modeling of proposed architectural solutions and new hardware features. - Writing architectural specification documents in collaboration with engineers across different subject areas. - Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives. - Improve Apple's performance modeling platform by developing APIs, tools, and optimal standard examples that can be used throughout the company. - Carefully analyze and present results to enable data-driven architecture and design. - Measure and analyze existing silicon and workloads. - Some international travel is required for this position.

Education & Experience

- MS or PhD in CS, EE, or related field.

Additional Requirements


Back to top