Posted: Nov 10, 2021
Role Number: 200204949
Do you have a passion for invention and self-challenge? Do you flourish with pushing the limits of what's considered feasible? As a member of our diverse team, you will find yourself at the center of a silicon design group responsible for crafting and productizing innovative cellular SoCs! Apple's world-class design and integration processes are driven by top notch integration engineers who own various blocks of the chip and coordinate with various teams to get all changes released to the database and production synthesized on the project scheduled delivery dates. This is a high transparency and critically significant role that requires collaborating with multi-functional groups, as well as an organized approach to coordinating tasks to consistently hit schedules with a quality design.
- This position requires detailed knowledge of the ASIC design flow, FE, Design Verification, synthesis, scripting and netlist generation. The ideal candidate will have the following background:
- Confirmed experience in ASIC design flow
- Consistent history of high performance designs in a high-volume production for low power applications
- Proven record of RTL design and timing closure on large sophisticated designs
- Expertise in:
- SOC IP integration and RTL Design for performance, low area, and low power
- FE production synthesis with DFT insertion
- ASIC design flow and netlist flow checks - Lint, CDC, Logical Equivalence
- UPF flow for defining power intent of chips with multiple power domains
- Design interfacing to PD for floorplanning and timing closure
- Strong social skills are a must as the candidate will connect with a lot of diverse groups within and outside the company
- Self starter, highly motivated, highly organized, and schedule driven is a must
- Familiarity with DFT and backend related methodology and tools is a plus
You will be responsible for the following: Coordinates definition, design, verification and development of SoC architecture. Supports all facets of SoC design flow from high-level design, RTL implementation, synthesis and physical design. Define chip level architecture, Perform logic design and system simulation. Top level integration of connectivity, system bus, peripherals and CPU IP. Working closely with physical design team to complete GDS. Develop and maintain methodology/flow/checks for your design. Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process.
Education & Experience
BSEE is required, MSEE/PhD preferred.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
- We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.