CAD Engineer - Timing for Gate-Level Flows & Methodologies

    • Austin, TX


Posted: Apr 24, 2020

Role Number: 200001330

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. In this highly visible role as a senior level member of the STA CAD Tech & Signoff team, you will be an integral part of the effort to maximize the performance of Apple silicon. You will be responsible for all aspects of timing including working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products.

Key Qualifications

  • Typically requires 5+ years of hands on experience in static timing analysis flows
  • Familiar with all aspects of STA of large high-performance SoC or Processor designs in deep sub-micron technologies
  • Proficiency in analysis, tools, and methodologies for timing closure
  • Good understanding of noise, cross-talk, OCV effects, margins, and constraints
  • Programming in Perl, Python, Tcl, C++ or other languages is a must
  • Good communicator who can accurately assess, describe issues to management and follow solutions through to completion
  • Familiarity with timing and power ECO techniques and implementation is a plus
  • Familiar with circuit modeling, including SPICE models and worst-case corner


Working with design teams to understand and debug issues related to constraints, flow scripts, and timing closure Facilitate and drive STA methodology changes to improve overall STA flows Create/maintain scripts and methods for timing analysis and power reduction Deep analysis of timing paths to identify key issues Implement infrastructure to facilitate data mining and visualization Help create timing and power ECO custom scripts for project tapeout Working with Physical Design team, highlighting issues and best practices Create documentation and help with guidelines/specs

Education & Experience

BSEE; MSEE preferred; PHD less years experience

Additional Requirements

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