CAD Engineer - Analog/UPF
Posted: Oct 15, 2019
Role Number: 200113020
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a senior member of our CAD team, you will architect, develop, maintain and enhance power intent methodology and solutions for our Analog, RF and mixed-signal designs related to Low Power cross domains, UPF, CPF, Liberty and its related domains. The role requires you to work with different technology nodes and provide flows/methodologies for the different tool sets. Working in our small CAD team, you'll be collaborating with Analog, AMS and RF circuit, methodology, Power, Timing and PD teams. The role will also involve partnering with layout design, technology, and 3rd party EDA tool vendors to drive and coordinate effort of developing and validating power intent flows, enhancing and validating low power checks and doing results analysis.
- Typically requires 10+ years of industry experience in low power analog, mixed-signal circuit analysis with emphasis on power intent checks and rules based on UPF/IEEE 1801 consistency checks, and power intent methodology.
- Proficiency with Liberty representation of macro and chip level blocks with additional background on various Liberty attributes for Analog/Digital domains.
- Detailed understanding on various power gating techniques used in analog, mixed-signal circuits including always ON power, gated power, LDO power, virtual power, PG function is required.
- Expertise in low power modeling of Power Switches, including switch conditions, Isolation cell tracing with isolation enable condition, Level Shifter configuration for low to high, single or multiple domain is desirable.
- Experience with various vendor tools including Conformal, LEQ its TCL command interface and debugging is required. Support with Incisive/Xcelium based co-simulation with UPF, RTL is useful. Additional knowledge with VCLP simulator and it functionality is an added bonus.
- Experience in evaluating simulation and environment related CAD tool/product applications and driving EDA vendors to meet design requirements
- Understand custom IC designs, and knowledge of Post-layout extraction.
- Understanding behavioral models for AMS circuits, experience in Verilog, RTL, and familiarity with PDK and Spice models is a plus.
- Efficient programming skills in Perl, TCL, SKILL language, Python, or Shell. Ability to provide automations for rapid and dynamic design needs. Knowledge in Perforce and/or regressions is preferred
- Knowledge in Virtuoso Schematic Editor, PDK, CDF, Callbacks, Netlisting, Virtuoso Environment is useful. Experience in Virtuoso Layout Editor, Virtuoso Constraints a plus
- Good written and verbal communication skills, and the ability to collaborate well across teams.
We are a small CAD team, so you will have an impact with the analog, mixed-signal, and RF circuit design teams by: - Solving issues related to power intent automation on Analog, RF and Microwave applications with tools on command-line and Virtuoso environment - Helping designers in solving tool problems related to UPF, IEEE 1801, Liberty, Conformal, VCLP and developing/supporting automation flows - Solving AMS (Analog-Mixed Signal) simulation design and modeling issues related to circuits, thereby influencing the advancement of a variety of technology nodes
Education & Experience
MS / PhD preferred in a technical discipline
Back to top