Sr. SI/PI Engineer
The right candidate will play a key role in the design and development of our next generation networking products for our world class data centers. Strong experience developing data center class networking products is a must.
The ideal candidate is a strong hands-on SI engineer with Ethernet networking experience in the areas hundred gigabit switching fabrics, 10/40/100/400 gigabit interfaces, embedded CPU subsystems, network processors, high speed DDR analysis, and power distribution networks. Previous experience in defining and designing modular chassis based products is required. Must have previous experience working with Asian ODM and JDM partners, both in development and in manufacturing.
You will have previous experience in signal integrity, power integrity, IEEE 802.3 and other standards compliance, as an SI lead in the networking field. This includes architectural definition, specification, key component selection, pre-layout SI simulation, post-layout SI simulation, stackup analysis, AC/DC power integrity, working closely with design engineers, mechanical engineers, and PCB designers, testing and measurement, and transition to manufacturing. Applying skills in simulation, timing analysis, power analysis, and channel analysis is expected.
- 10+ years' experience in signal integrity
- Experience using DDR simulation tools such as Hyperlynx DDRx Wizard
- Hands-on experience in working with ODM/JDM partners and key component partners to deliver quality SI results, this includes training and guidance to use the tools and debug violations
- Experience as a project and technical lead, program management skills is a must
- Experience interfacing and leading cross functional teams such mechanical engineers, test engineers, and process engineers
- Strong knowledge of wave propagation, transmission line impedance analysis, crosstalk, return loss, insertion loss, terminations, eye patterns, jittler analysis, multi-GHz channel analysis, and S-parameters
- Strong knowledge of power distribution network analysis, both AC and DC, decoupling strategies, and techniques for mitigation of simultaneous switching noise
- Strong knowledge of Ethernet IEEE 802.3 compliance, CDE, ESD, and surge protection
- Strong experience with impedance, TDR, and VNA measurement techniques and equipment
- Understands the tradeoffs between designing for cost and performance
- Good verbal and written communication skills, must be organized
- Candidate should be able to accommodate approximately 33% travel to both Seattle/Cupertino and Asia. Candidate must be able to enter both Taiwan and China without visa issues.
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