RTL Design Engineer


Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Hardware Design Engineers to work with partners and vendor and build the next generation of our cloud server infrastructure. Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies.

As a member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you'll work with thought leaders in multiple technology areas. You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve your products performance, quality and cost. We're changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.


  • Develop detailed design specifications
  • Perform RTL coding
  • Instruct Physical design team with physical constraints, timing analysis and signoff responsibilities for your Block/s
  • Lead our PCIe technology efforts
  • Run industry standard code quality tools and fix issues found by them
  • Participate in test plan and coverage reviews
  • Communicate and work with team members across multiple disciplines
  • Participate in SoC Lab testing of the product, specifically for PCIe standard testing and debugging in Lab

Basic Qualifications

  • BS degree or higher in EE, CE, or CS
  • 10 years of practical experience with SoC design
  • Practical experience working with PCIe
  • Experience working with 3rd party development projects
  • Experience with design development using Verilog
  • Experience with design verification, synthesis, timing/power analysis
  • Excellent verbal and written communication skills

Preferred Qualifications

  • Experience with PCIe SERDES
  • Experience with wide variety of low power design techniques
  • Large breadth of knowledge from architecture through physical design
  • Knowledge of FPGA and emulation platforms
  • Proficient with writing automation scripts
  • Experience with PCIe lab debugging and PCIe protocol Analyzer usage

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