ASIC verification engineer
- Taipei, Taiwan
Blink was the result of one of the most successful crowdfunding campaigns ever and is now part of Amazon Devices, the consumer electronics division that brings you the Kindle, Fire Tablets, Fire TV, and Echo. Our mission is to provide peace of mind for home owners while they are way from home using our wire-free, battery-operated smart home security cameras.
Our vertically integrated engineering team works on algorithms, ASICs, hardware, firmware, cloud software, and mobile applications to deliver smart-home products that customers love. We are looking for exceptionally bright and entrepreneurial-minded Sr. ASIC Verification Engineers to join our fast growing team.
As Sr. ASIC Verification Engineers, you will be part of Blink ASIC team, and your responsibilities will include building verification infrastructure and environment, constrained-random testing, end-to-end SoC testing, block-level RTL design testing, and verification closures including code and functional coverages.
• Work on verification plans of complex digital design blocks and SoCs by fully understanding the system design architecture and functional specifications
• Interact and communicate with logic design engineers to identify important verification scenarios
• Conduct all phases of verification process including simulations, test bench development, and verification documentation
• Create and enhance constrained-random verification environment using SystemVerilog, C/C++, and industry leading verification methodologies
• Organize coverage measures and test cases for stimulus and functional corner-cases
• Bachelor's degree in Electrical Engineering or Computer Science
• Experience in verifying RTL digital logic designs for ASICs using SystemVerilog or Verilog
• Experience in digital design with understanding of design-for-verification methodologies
• Experience in defining, constructing, and using verification components and environments with standard verification methodology
• 5+ years of experience in creating test plans, writing test cases, running simulations, and debugging RTL designs by closely working with logic designers
• 5+ years of experience involved and contributed to at least 2 ASIC tapeouts
• Excellent communication skills and ability to work in cross-functional teams
• Master's in Electrical Engineering or Computer Science
• Experience with image processing, audio processing, computer vision, and/or machine learning applications
• Experience in gate-level simulation and verification
• Experience of ASIC bring-ups and post-silicon validations
• Knowledge of verification techniques including UVM
• Debug tests by working closely with design engineers to deliver functionally correct designs , and achieve 1st-pass successes for ASICs and SoCs
• Construct measures to eliminate verification holes by 100% code and functional coverages
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