RTL Design Staff Engineer
- San Francisco, CA
As part of Accenture's Industry X, the Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands on experience in architecture, logic design, verification, physical design, emulation and firmware . We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true "Silicon to SW" Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
Whether at our Silicon Design Center in Phoenix or at one of our other locations you will get to collaborate and innovate with the world's leading product development companies. In our dynamic fast-paced environment you will get to make the impossible possible.
Accenture is invested in our team member's growth and provide many opportunities for training and skills expansion.
The RTL Designer will be required to
- Contribute to the development of efficient µArchitectures and contribute to ASIC Architecture, design and verification
- Understand our in-house IPs needed and how they need to be integrated, connected and verified
- Drive the top-level µArchitecture definition and develop the necessary RTL
- Drive the chip-level integration, verification plan development and verification
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
- Support the test program development, chip validation and chip life until production maturity
- Work with FPGA engineers to perform early prototyping
- Support hand-off and integration of blocks into larger SOC environments
- Assist with Algorithm analysis, verification and improvement
- Contribute to ASIC digital architecture, design and verification
- Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Science or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience)
- 1 year of experience in RTL coding, synthesis and/or SoC Integration
- Experience as a Digital Design Engineer or Chip Lead
- Knowledge in uP and/or GPU and/or Video Processing
- Experience in RTL coding, synthesis and/or SoC Integration
- Experience in digital design µArchitecture
- System Verilog OVM/UVM experience
- Python (or similar) scripting experience
- Experience in SoC integration and ASIC architecture
- Experience in DFT/Testability requirement and test program definition
- Experience using High Speed interfaces like PCIe, USB, MIPI
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.
Equal Employment Opportunity Statement
Accenture is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion or sexual orientation. Our rich diversity makes us more innovative, more competitive and more creative, which helps us better serve our clients and our communities.
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Other Employment Statements
Candidates who are currently employed by a client of Accenture or an affiliated Accenture business may not be eligible for consideration.
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Locations CA - San Francisco,CA - San Jose
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