RTL Design Engineer
- San Francisco, CA
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People in our Client Delivery & Operations career track drive delivery and capability excellence through the design, development and/or delivery of a solution, service, capability or offering. They grow into delivery-focused roles, and can progress within their current role, laterally or upward.
In this position, you would be working within Accenture Products and Platforms (APP). APP operates a portfolio of product-mindset business units inside Accenture - each with a shared mission to codify industry and functional knowledge into valuable and differentiated software assets for sale to Accenture clients or as market-facing products in clients' own offerings. APP teams overlay Pragmatic frameworks and Agile methodologies to create value and deliver excellence every day. APP products and platforms accelerate time-to-value, ensure customer satisfaction, and drive productive, long-term client engagements. APP offers unique and rewarding opportunities and software career paths within Accenture.
We are looking for a RTL Lead Engineer responsibilities include:
- Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
- Understand our in-house IPs needed and how they need to be integrated, connected and verified
- Drive the top-level µArchitecture definition and develop the necessary RTL
- Drive the chip-level integration, verification plan development and verification
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
- Support the test program development, chip validation and chip life until production maturity
- Work with FPGA engineers to perform early prototyping
- Support hand-off and integration of blocks into larger SOC environments
- Assist with Algorithm analysis, verification and improvement
- Contribute to ASIC digital architecture, design and verification
- Ability to communicate clearly
- Bachelors Degree in Electrical Engineering or Computer Science or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience)
- 5 years of experience as a Digital Design Engineer and/or a Chip Lead
- Experience in RTL coding, synthesis and/or SoC Integration
- Experience in digital design µArchitectureSystem Verilog OVM/UVM experience
- Python (or similar) scripting experience
- Python-embedded HDL - Magma will be a preferred qualification
- Experience in SoC integration and ASIC architecture
- Experience in DFT/Testability requirement and test program definition
- Experience using High Speed interfaces like PCIe, USB, MIPI
- Masters degree in EE
- Experience in AI and/or ML algorithm development
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.
Accenture is an EEO and Affirmative Action Employer of Females/Minorities/Veterans/Individuals with Disabilities.
Equal Employment Opportunity: All employment decisions shall be made without regard to age, race, creed, color, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.
Job candidates will not be obligated to disclose sealed or expunged records of conviction or arrest as part of the hiring process.
Accenture is committed to providing veteran employment opportunities to our service men and women.
Candidates who are currently employed by a client of Accenture or an affiliated Accenture business may not be eligible for consideration.
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