ASIC Design Verification Sr. Staff Engineer
- Phoenix, AZ
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People in our Client Delivery & Operations career track drive delivery and capability excellence through the design, development and/or delivery of a solution, service, capability or offering. They grow into delivery-focused roles, and can progress within their current role, laterally or upward.
In this position, you would be working within Accenture Products and Platforms (APP). APP operates a portfolio of product-mindset business units inside Accenture - each with a shared mission to codify industry and functional knowledge into valuable and differentiated software assets for sale to Accenture clients or as market-facing products in clients' own offerings. APP teams overlay Pragmatic frameworks and Agile methodologies to create value and deliver excellence every day. APP products and platforms accelerate time-to-value, ensure customer satisfaction, and drive productive, long-term client engagements. APP offers unique and rewarding opportunities and software career paths within Accenture.
We are looking for SoC Design Verification Engineer to provide design verification
services for multi CPU/DSP SoC.
- Testbench development - System Verilog UVM and C tests
- Integration/development of C tests/APIs and SW build flow
- Integration/development of UVM mailboxes and HW/SW communication components
- Integration of lower level UVM testbenches
- Test plan development
- Power Aware testbench development and simulations
- Seamless porting between simulation/emulation/prototyping platforms
- Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
- Coverage collection and closure
- Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Basic Qualifications :
- Minimum of 5+ years of experience in RTL Design and Verification area of which
- Minimum of 2+ years of experience in SoC Design Verification and HW/SW verification
- Minimum of 2+ years within any of the following:
- System Verilog UVM and vertical tetsbench integration
- Low level HW/SW interaction and debug
- M ulti CPU and debug architectures
- D evelopment of fully automated flows
Preferred Qualification :
- Experience with low level SW debug - disasm, Tarmac, trace
Experience with coresight architecture
Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
Experience with coverage merging across simulation and emulation
Experience with Power Aware and Gate Level Netlist in Emulation
- Experience with development of fully automated flows
- Experience with Gate Level Simulations
- Python Scripting
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.
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Candidates who are currently employed by a client of Accenture or an affiliated Accenture business may not be eligible for consideration.
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